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juchibo
用vhdl语言生成锯齿波,数据可自行改变(Sawtooth wave with vhdl language generation, the data can change by itself)
- 2011-12-21 19:29:51下载
- 积分:1
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vhdl,无进位同步计数器,完成6进制加,输出6进制序列数
vhdl,无进位同步计数器,完成6进制加,输出6进制序列数-vhdl, non-binary synchronous counter to complete the six binary Canada, output 6, the number of binary sequences
- 2022-09-12 08:25:03下载
- 积分:1
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verilog full case and paralel case directive usage
verilog full case and paralel case directive usage
- 2022-05-28 07:00:24下载
- 积分:1
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steper motor
说明: stepper motor module on spartan 6 and 24MHz clock fequency
- 2019-03-10 15:44:31下载
- 积分:1
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QC_LDPC译码器的FPGA设计
说明: LDPC码的FPGA实现,用verilog语言编写(FPGA implementation of LDPC code, written in Verilog language)
- 2019-11-15 06:04:33下载
- 积分:1
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4bit-adder_verilog
4位全加法器的modelsim工程带testbench(Four full-adder modelsim project with testbench)
- 2020-08-16 16:38:25下载
- 积分:1
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SHUMAGUAN
FPGA 点亮数码管的灯,本例程支持6位数码管,因为我的FPGA开发板是这样子的(The lamp of digital tube illuminated by FPGA)
- 2020-06-18 10:20:02下载
- 积分:1
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DDR3读写测试
MIG IP控制DDR3读写测试,于MIG IP核用户接口时序较复杂,这里给出扩展接口模块用于进一步简化接口时序。(MIG IP controls DDR3 reading and writing tests, and the time sequence of MIG IP kernel user interface is more complex.)
- 2018-03-28 16:01:36下载
- 积分:1
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xc3s400芯片详细的英文资料,xc3s400的FPGA开发板使用者必看
xc3s400芯片详细的英文资料,xc3s400的FPGA开发板使用者必看-chip xc3s400 detailed information in English, xc3s400 the FPGA development board users see
- 2023-09-02 13:00:04下载
- 积分:1
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BFSK-BPSK-QPSK-DPSK
文件中包含BFSK、DPSK、BPSK、QPSK等等数字调制程序。(File contains the BFSK, DPSK, BPSK, QPSK, and so on digital modulation process.)
- 2013-03-20 16:28:11下载
- 积分:1