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说明: 单周期cpu,使用verilog编写的的单周期cpu支持......等功能(Single cycle CPU, using Verilog written single cycle CPU support... And other functions)
- 2021-03-15 08:45:07下载
- 积分:1
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USB2.0的VHDL描述,很经典了,欢迎大家下载
USB2.0的VHDL描述,很经典了,欢迎大家下载-USB2.0 the VHDL description, very classic, and welcomes everyone to download
- 2023-04-17 09:30:03下载
- 积分:1
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对与单片机常用的功能看门狗,本程序用vhdl硬件语言实现次功能。...
对与单片机常用的功能看门狗,本程序用vhdl硬件语言实现次功能。-Commonly used with single-chip watchdog function, the procedures for using VHDL hardware language functions realize times.
- 2022-05-25 08:46:37下载
- 积分:1
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16 point radix 2
使用 c languageit 的 16 点基 2 fft 代码将 16 点时间域序列转换为频率域
- 2022-10-05 23:25:03下载
- 积分:1
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adder.ripple
an 16 bit ripple carry adder
- 2012-11-02 23:20:33下载
- 积分:1
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CH372
USB设备接口的驱动程序,采用verilogHDL语言编写,并包含相关说明资料(USB device driver interface, using verilogHDL language, and contains descriptive information)
- 2014-01-03 02:23:08下载
- 积分:1
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Can be directly downloaded to the chip used in the complete UART with FIFO proce...
可以直接下载到芯片用的带有FIFO的完全UART程序,vhdl语言编写。-Can be directly downloaded to the chip used in the complete UART with FIFO procedures, vhdl language.
- 2022-05-23 23:16:30下载
- 积分:1
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FPGA源代码
FPGA源代码公布,包括多进制数字频率调制VHDL程序FPGA驱动LCD显示中文字符“年”程序,LED静态显示ADC0809 VHDL控制程序,DAC0832 接口电路程序
- 2022-04-26 16:23:11下载
- 积分:1
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DE2_NIOS_HOST_MOUSE_VGA
基于nios的vga显示实验,自制的ip核。可以按照自己的需求改写ip(Nios to vga display ip nuclear experiments, homemade. Can be rewritten in accordance with their own needs ip)
- 2021-04-11 11:58:58下载
- 积分:1
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hssdrc IP核的可配置的通用SDRAM控制器的自适应银行…
HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline.
HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim.
HSSDRC IP core is licensed under MIT License
- 2022-09-20 22:10:03下载
- 积分:1