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DA
说明: DOCUMENT ON DISTRIBUTED ARITHMATIC
- 2014-02-05 17:06:51下载
- 积分:1
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译码器,将八位输出转换为七段译码显示,相当于7448驱动译码管...
译码器,将八位输出转换为七段译码显示,相当于7448驱动译码管-Decoder, the 8 output is converted to seven segment decoding shows that the equivalent of 7448
- 2022-05-30 05:04:27下载
- 积分:1
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half_band
半带滤波器verilog源代码,主要用于采样率变换系统中,采用乘法积累加器,很好的例子,供大家参考(Half band filter verilog code, mainly for the sampling rate conversion system, use the multiplication accumulation adder, a good example, for your reference)
- 2020-12-23 10:59:07下载
- 积分:1
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fifo
说明: 用FPGA完成256*8的存储器的读写操作( complete reading and writing 256* 8 memory with FPGA )
- 2010-04-24 17:07:06下载
- 积分:1
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AHDL
AHDL语言介绍,很详细的介绍AHDL语言介绍,很详细的介绍(AHDL language introduction, a detailed explanation)
- 2009-11-17 15:27:59下载
- 积分:1
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telephone-cost-metering
该程序用来实现电话计时以算取费用,比较简单(telephone cost metering verilog code)
- 2013-11-03 19:45:00下载
- 积分:1
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这是用VHDL编写的译码程序,程序简单易懂
这是用VHDL编写的译码程序,程序简单易懂-VHDL prepared decoding procedures that are simple to understand
- 2022-01-25 21:28:32下载
- 积分:1
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针对于Virtex5FPGA的DDR2读写测试的完整工程
资源描述针对于Virtex5FPGA的DDR2读写测试的完整工程,已测试可以使用,可以根据自己的ddr2配置自行更改。。。。
- 2023-02-19 21:40:05下载
- 积分:1
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log10(x)
Fixed-point base-2 logarithm (DW_log2)
// Computes the base-2 logarithm of a fixed point value in the
// range [1,2).
- 2014-09-11 19:58:10下载
- 积分:1
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LVDS_RX
说明: lvds_rx IP核硬件设计代码,使用时注意LVSD_RX模块的延时参数的设置,3.5倍时钟相位的设置(Lvds IP core hardware design code, when using the attention LVSD module delay parameter settings, 3.5 times the clock phase settings)
- 2021-04-26 11:38:45下载
- 积分:1