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Applicable to FPGA
适用于FPGA的SOPC方面的元器件添加，如COMPNENT-Applicable to FPGA-SOPC area to add components, such as COMPNENT
- 2023-06-04 02:30:03下载
- 积分：1
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Electric Guitar Digital Effects Processor
Electric Guitar Digital Effects Processor
- 2022-11-09 05:15:03下载
- 积分：1
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DE2 FPGA盒
FPGA KIT DE2-35
This project outputs a selected voltaje using VGA DAC, the DAC module is controlled using LCD display and buttons.
- 2022-12-31 09:25:04下载
- 积分：1
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LAB-9
LAB 9, Excercise for DE2 Altera
- 2014-11-28 11:50:00下载
- 积分：1
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div_fru
介绍分频器的好资料。不光有奇数分频、偶数分频，还有小数分频。相信把这个资料理解透了后以后分频器的设计就不是问题了。(Introduction divider good information. Not only have an odd frequency, even frequency, there are fractional. I believe understanding this information through the post after the Divider is not a problem.)
- 2010-06-17 21:52:55下载
- 积分：1
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巴克内尔Verilog手册
Bucknell Verilog Manual
- 2022-02-02 15:04:14下载
- 积分：1
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TOPSWITCH
TOPSWITCH-Ⅱ系列芯片在功率集成开关电源中应用的研究-TOPSWITCH-Ⅱ series of chips in the power switching power supply in the application of integrated research
- 2022-04-27 21:12:27下载
- 积分：1
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Dec_mul
时间同步后即可确定每帧数据的起始位置，这样就能完整的截取下每一帧。但是，数据中还带有频偏信息。在常规的通信系统中，多普勒很小仅仅会带来很小的频偏，但是在大多普勒的情况下，频偏将非常大，20马赫的速度将会带来将近34K的频偏。因此，如何很好的纠正频偏即为本系统的难点。
OFDM中，我们将大于子载波间隔倍数的频偏称为整数倍频偏，而将小于一个子载波间隔的频偏称为小数倍频偏。频偏矫正精度只要能保证小于十分之一倍的子载波间隔，频偏就不会对均衡和解调造成影响。本文中我们借鉴这种思想，由于硬件资源限制，我们将在接收端做64点FFT，即相当于将频域划分为64份，我们将小于 的频偏称为小数倍频偏，将 整数倍的频偏称为整数倍频偏。本程序即基于SCHIMDL经典方法完成小数倍频偏纠正(After time synchronization can determine the starting position of each frame data, so you can complete the interception of each frame. However, in the data with frequency information. In conventional communication systems, doppler small will bring only small deviation, but in the case of most of the doppler, frequency PianJiang is very large, 20 Mach speed will lead to deviation of nearly 34 k. Therefore, how to good to correct deviation is the difficulty of this system.
OFDM, we will be bigger than the sub-carrier spacing ratio of frequency deviation is called the integer frequency offset, and the interval will be less than a child carrier frequency offset is called decimal frequency doubling. Deviation is less than one over ten times as long as can guarantee accuracy of sub-carrier spacing, deviation will not affect balance and demodulation. This article, we draw lessons from the idea, due to the limited hardware resources, we will do 64 points FFT at the receiving end, which is equ)
- 2013-12-26 18:00:24下载
- 积分：1
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RANGEN
2011年全国大学生电子设计竞赛E题“简易数字信号传输性能分析仪”fpga的控制代码，verilog编写；包括了M序列及同步时钟的提取等所有程序。(2011 National Undergraduate Electronic Design Contest E title "Simple digital signal transmission performance analyzer" fpga control code, verilog prepared including the M-sequence and synchronous clock extraction and all other programs.)
- 2020-10-27 17:09:59下载
- 积分：1
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Ver_I2C_eeprom
用verilog编写的I2C——E2PROM模型。适用于各种型号的E2PROM，代码内部有参数可选。(Written in verilog I2C- E2PROM model. E2PROM, the internal code applicable to various types of optional parameters.)
- 2013-04-10 16:14:03下载
- 积分：1
