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key_xiaodou
说明: 该资料是用vhdl编写的按键消抖程序,按键消抖在使用按键的数字电路中非常重要,如果不对按键信号进行处理,有可能会出现大量错误的按键信号。文件key_xd.vhd是按键消抖程序,文件key_xd.vwf是仿真波形文件。该程序已经通过仿真测试,并且在电路板上调试通过,效果理想。(The information is written in the key consumer vhdl shaking procedures, key consumer shaking in digital circuits using the buttons is very important, if not key signal processing, there may be a lot of the wrong button signal. File key_xd.vhd is key consumer shake procedure is the simulation waveform file key_xd.vwf file. The program has been tested by simulation and debugging in circuit board by, the results are satisfactory.)
- 2010-04-26 16:13:57下载
- 积分:1
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CODE_VHDL_COUNTING 电路时钟运动显示期间 LED 7 (MẠCH ĐẾM ĐỒNG HỒ THỂ 邵族 HIỂN THỊ 领导 7 ĐOẠN)
CODE_VHDL_COUNTING 电路时钟运动显示期间 LED 7 (MẠCH ĐẾM ĐỒNG HỒ THỂ 邵族 HIỂN THỊ 领导 7 ĐOẠN)
- 2022-01-25 22:02:59下载
- 积分:1
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Avt_S6LX9_MicroBoard_UCF_110127
Avt_S6LX9_MicroBoard_UCF_110127,有关xilinx spartan6开发板的相关参考设计。(Adding Custom IP to an Embedded System, the relevant reference on xilinx design.)
- 2013-07-03 11:26:20下载
- 积分:1
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这是我用vhdl语言,在fpga内部做了一个双口ram的程序。我的邮箱:wleechina@163.com...
这是我用vhdl语言,在fpga内部做了一个双口ram的程序。我的邮箱:wleechina@163.com-This is the language I used vhdl in fpga done an internal dual-port ram procedures. My mail : wleechina@163.com
- 2022-05-06 16:15:30下载
- 积分:1
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VERILOG HDL 实际工控项目源码
开发工具 altera quartus2
VERILOG HDL 实际工控项目源码
开发工具 altera quartus2-verilog HDL actual industrial projects source development tools altera quartus2
- 2022-02-07 05:53:32下载
- 积分:1
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FIFO
FIFO的源代码,对FIFO设计有帮助,有借鉴意义,帮助学习VHDL编程(FIFO of the source code, on the FIFO design help, there is reference to help learn VHDL programming)
- 2008-04-29 09:00:11下载
- 积分:1
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这是个vhdl编写的16bit的加减法器
这是个vhdl编写的16bit的加减法器-This is vhdl prepared by the modified instruments used in the 16bit
- 2022-02-15 07:17:54下载
- 积分:1
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是用于pci开发的核,可以将硬件的信息映射到然间上来 节省出开发人员用于了解硬件的时间...
是用于pci开发的核,可以将硬件的信息映射到然间上来 节省出开发人员用于了解硬件的时间 -Pci developed for nuclear, hardware information can be mapped to the inter-ran up to save the developers time to understand the hardware
- 2022-01-26 02:12:56下载
- 积分:1
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四位十进制频率计的顶层控制模块,用于生成测频需要的复位及控制信号...
四位十进制频率计的顶层控制模块,用于生成测频需要的复位及控制信号-four decimal frequency of top-level control modules, used to generate the required frequency measurement and control signals reset
- 2022-07-22 04:02:23下载
- 积分:1
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出租车计价器VHDL程序与仿真 的vhdl源代码
出租车计价器VHDL程序与仿真 的vhdl源代码-Taximeter VHDL procedures and simulation vhdl source code
- 2022-03-29 12:46:57下载
- 积分:1